Polycrystalline silicon (polysilicon) resistors are commonly used as load devices in a variety of digital and analog applications, and in particular, in Static Random Access Memories (SRAMs). SRAM cells with resistive loads are hereafter referred to as the 4D/2R SRAM cells. Stacking polysilicon load resistors above the NFETs in 4D/2R SRAM cells can be advantageously used in the layout of an SRAM chip. This results in significant reductions in the SRAM cell size because the cell area is then only determined by the area used by the NFETs. It has become now a common practice in the industry to have the load resistors of 4D/2R SRAM cells formed by resistive polysilicon lands obtained from a very thin layer of either intrinsic or lightly doped polysilicon material. However, because these load resistors must be fairly high-valued, say in the tera-ohms 10.sup.12 .OMEGA. range and above, in order to decrease the current drawn by the cell, capacity of 4D/2R SRAM cell chips appears to be limited to the 1 megabit range. As a matter of fact, for increased capacities, the polysilicon layer would be so thin that the process tolerances would be too difficult to control. Moreover, 4D/2R SRAM cells are also very sensitive to soft errors produced by alpha particles. Beyond the 1 megabit range, stacked PFETs (rather than polysilicon resistors) should be used as load devices, although this is achieved at the cost of a significantly more complete manufacturing process.
FIG. 1 shows a conventional 6D SRAM cell circuit referenced 1 with PFETs as load devices. Two cross-coupled NFETs N1 and N2, so-called driver transistors, are connected between common node 2 attached to a first supply voltage Vs (usually, ground Gnd) and respective nodes 3 and 4, so-called charge storage nodes. These nodes 3 and 4 are connected to a common node 5 attached to a second supply voltage (usually a positive voltage Vc), respectively, through PFETs P1 and P2. On the other hand, nodes 3 and 4 are also respectively connected to the bit lines BLT and BLC through NFETs N3 and N4, so-called access transistors. The gate electrodes of NFETs N3 and N4 are connected to the word line WL for READ and WRITE operations.
FIG. 2 is a partial cross-sectional view of the structure of the 6D SRAM cell circuit of FIG. 1. This structure is integrated in a semiconductor substrate according to a conventional CMOS manufacturing process offering stacked polysilicon gate PFET devices (sPFETs). The structure 6 provides a good example of the state of the art and is extracted from an article entitled: "A 0.1 .mu.A stand-by current ground-bounce-immune 1-M bit CMOS SRAM by M. Ando et al, published in the IEEE JSSC, Vol. 24, N.degree. 6, Dec. 1989, pp. 1708-1713. Reference numeral 7 indicates the P type silicon substrate, whereas 8 indicate the different field recess oxide (ROX) regions that are used to isolate the different active regions of the structure. Numerals 9 are active N+ implanted source and drain regions of the NFETs; 10 shows the gate dielectric layer, typically an SiO.sub.2 layer. The highly doped N+ polysilicon gate electrodes of driver NFETs N1 and N2 are respectively referenced as 11-1 and 11-2. Polysilicon gate electrode 11-2 forms a buried contact with region 9' which is a protrusion of the drain region 9 of NFET N1. The gate electrodes 11-1 and 11-2 and the source and drain regions of NFETs N1 and N2 are covered by a thin insulating protective layer 12 of SiO.sub.2 2 which forms oxide sidewalls or spacers on the lateral sides of gate electrode 11-1 of NFET N1. A polysilicon land 13 surmounts gate electrodes 11-1 and 11-2 and is isolated from the gate electrodes by the SiO.sub.2 layer 12. Polysilicon land 13 results from the patterning and selective doping of an intrinsic or lightly doped polysilicon layer that has been deposited to form the body of sPFETs. As apparent from FIG. 2, this polysilicon land 13 is highly doped with a P type dopant except in the region above gate electrode 11-1. The undoped region forms the channel region of the sPFET P1 while the adjacent P+ doped regions form the source and drain regions thereof. An extension of the drain region of sPFET P1, so-called the extended drain region, contacts the small portion of gate electrode 11-2, which is exposed through an opening in oxide layer 12. N+ doped gate electrode 11-1 of NFET N1 also plays the role of gate electrode of sPFET P1, while layer 12 is the gate dielectric thereof. More generally, for each cell, oxide layer 12 is opened in all locations where it is necessary to make a contact between the N+ doped polysilicon gate electrode of a NFET and the adjacent P+ extended drain region of the corresponding sPFET. Note that region 9 and protrusion thereof 9', gate electrode 11-2 and the extended drain region of sPFET P1 13 are at the potential of node 3, achieving thereby the desired cross-coupling of the devices, as illustrated in the cell circuit of FIG. 1. At this stage of the process, the structure is said to have completed the Master Slice processing steps of a polysilicon gate CMOS FET technology. The structure is passivated by a relatively thick, insulating SiO.sub.2 layer 14, about 500 nm thick. As such, the structure results from the FEOL (Front End Of the Line) processing.
Elements that will now be described are formed during the personalization steps or BEOL (Back End Of the Line) processing. Numeral 15 is a typical example of a polycide land or line used as a power bus. In FIG. 2, polycide land 15 which connects a N+ active region 9 (the source region of a NFET not illustrated in FIG. 2) to Gnd to be called thereafter the Gnd bus. An additional insulating SiO.sub.2 layer 16 completes the structure. Layer 16 is provided with contact openings (not shown) to allow appropriate contacting between metal bit lines BLT and BLC and power busses (e.g., Vc power bus). As apparent from FIG. 2, all succeeding layers, and in particular polysilicon layer 13, are conformally deposited, which results in the typical "corrugated" relief aspect of the upper layers of structure 6.
The cell construction of FIG. 2 wherein the PFETs are used as loads and stacked above the NFETs, is of great interest in terms of density, because the cell area is only determined by the area of NFETs. However, the disclosed semiconductor structure and its corresponding manufacturing process have some drawbacks that are listed below.
1. The structure of FIG. 2 needs for its fabrication six more additional masks with respect to a conventional manufacturing process of 6D SRAM cell chips not offering sPFETs in the menu. The first mask is used to remove the gate oxide layer 10 above protruded source region 9' of NFET N1 to allow the buried contact between gate electrode 11-2 and region 9'. The second mask makes an opening above gate electrode 11-2. The third mask delineates the N type lightly doped polysilicon layer 13. The third mask is used to shape the desired polysilicon land wherein sPFET P1 and its related extended drain region (for connection with underlying gate electrode 11-2) are formed. The fourth mask is a block-out mask that is required to protect the channel region of sPFET P1 from implantation of P type dopants, while forming the highly doped P+ source and drain regions thereof, along side the extended drain region. The fifth mask defines contact openings where polycide lands conveying the Gnd potential contact source regions 9 of certain NFETs, e.g., driver transistors (not referenced). An example of a Gnd bus is shown in FIG. 2. Finally, the sixth mask delineates said polycide lands, comprised of word lines and some power busses. PA0 2. sPFET P1 depends on the underlying NFET N1 size and layout, which in turn results in less flexibility in the design. Because the gate electrode 11-1 of NFET N1 is also the gate electrode of sPFET P1, the layout of the two devices are strongly coupled both in terms of device size and device layout. More generally, since the gate length of the NFET, e.g. N1, must be at the minimum allowed by the lithography for maximum performance, so must be the gate length of the corresponding sPFET, e.g., P1. This constitutes a potential source of reliability hazards. Firstly, if the out-diffusion of the P+ dopants contained in the implanted source and drain regions of the sPFET P1 is not well controlled, the source and drain regions become too large, thereby reducing the effective channel length of sPFET P1. As a consequence, punch-through problems can occur. The channel length of sPFET P1 cannot be increased since this length is dictated by the performance requirements of NFET N1 as mentioned above. In addition, since the block-out mask defining the channel region of sPFET P1 is also at minimum image size, alignment tolerance between this block-out mask and the channel region can result in a channel region not correctly aligned with the gate electrode. FIGS. 3A and 3B illustrates the effect of misalignment on sPFET P1 as to the introduction of parasitic devices to an ideal PFET P (that would be obtained, should misregistration not exist) that has inherently a poor performance. In the first case (positive misalignment) shown in FIG. 3A, diode D (forwardly-biased) and a high value resistor R are in series with the source region s of the ideal PFET P. These parasitic devices decrease the effective gate to source overdrive voltage (VGS-VT) of sPFET P1 (which already has a high threshold voltage VT), and hence will decrease the "ON" current of sPFET P1. In the second case (negative misalignment), shown in FIG. 3B, the parasitic devices: e.g. resistor R and diode D (now reversely-biased) are in series with the drain region d of the ideal PFET P, and similarly decrease the current capability of sPFET P1. As a result, the latter is far from an ideal PFET P. PA0 3. The gate electrode of the sPFET P1 does not have an optimized work function. Since both NFET N1 and the corresponding sPFET P1 formed thereupon share the same N+ gate electrode 11-1, the gate electrode of the sPFET is therefore of the N+ type, while P+ type would have been preferred. It is well recognized that this situation creates some punch-through problems because the channel region is buried instead of being at the surface. Punch-through effects induce leakage currents which are critical to cell stand-by power consumption of the SRAM cell. PA0 4. As previously mentioned in reference to FIG. 2, the conventional manufacturing process results in a non planarized structure 6. The gate oxide layer 12 and the polysilicon layer 13 forming sPFET P1 are deposited over the castellated topology of the NFET N1 gate electrode 11-1 although slightly smoothed by protective layer 12, thereby creating reliability problems, known as "step coverage" (since polysilicon layer 13 is much thinner than gate electrode 11-1). PA0 5. A parasitic P+/N+ diode is formed between N+ gate electrode 11-2 of NFET N2 and the P+ extended drain region of sPFET P1. This diode deteriorates the contact quality which is no longer of the ohmic type, thereby slowing down the SRAM cell performance. PA0 6. The word lines WL, some power busses and possibly the local interconnect scheme that makes straps and short distance connections at the silicon wafer level, are made of polycide. Polycide is a good conductive material; however it is known to exhibit higher resistivities than metal. PA0 7. Finally, the structure of FIG. 2 has poor design flexibility because of the difficult contacting of source region of sPFET P1 to Vc power bus in the presence of polycide lands 15. PA0 a) depositing a first thick passivating layer of a dielectric material that can be planarized onto the base structure; PA0 b) forming a set of first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; PA0 c) depositing a first layer of a conductive material to fill the first stud openings and define a set of first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; PA0 d) planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; PA0 e) depositing a thin insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; PA0 f) depositing a layer of polysilicon lightly doped with an impurity of a first type of conductivity; PA0 g) patterning the polysilicon layer to define a plurality of polysilicon lands contacting the first contact studs at the desired locations; PA0 h) selectively implanting ions of a second type of conductivity dopant in the structure to define the source and drain regions of the PFET devices and interconnection conductors in certain polysilicon lands or portions thereof; PA0 i) depositing a cap layer; PA0 j) depositing a second thick passivating layer of a dielectric material that can be planarized; PA0 k) forming a set of second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; PA0 l) depositing a second layer of conductive material to define a second set of second contact studs; PA0 m) planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.